Originally Posted by crane
A simple way to implement failsafe hardware priorities is with PFETs. If your RIMS has priority over the HLT the connect the source of the PFET to the HLT control output and the gate to the RIMS control output. Finally connect the drain to the input of your SSR. This way the input to the HLT SSR will only be high when the HLT output is high and the RIMS output is low. This way you don't need those fancy logic gates that require their own power and ground connections. KISS
To expand this idea for your 3rd vessel you will need 2 more PFETs. The gate of PFET1 will be connected to the RIMS control output and the gate of PFET2 will be connected to the HLT control output. The source of PFET1 will be connected to the BK control output. The drain of PFET1 will be connected to the source of PFET2 and finally the drain of PFET2 will be connected to the BKs SSR input. This way the only time the BK will be on is when both RIMS and HLT control outputs are low and BK control output is high.